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[VHDL-FPGA-Verilog] bbb

Description: AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.
Platform: | Size: 216064 | Author: sss | Hits:

[Other Embeded program] rgb2yuv

Description: verilog编写，rtl风格，流水线设计，实现图像rgb格式到yuv格式的转换。-Verilog prepared, rtl style, pipeline design, realize image rgb to yuv format format conversion.
Platform: | Size: 1024 | Author: 苗苗 | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[SCSI-ASPI] dlx_verilog

Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
Platform: | Size: 9216 | Author: 李乔 | Hits:

[VHDL-FPGA-Verilog] FIFO_8_8

Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Platform: | Size: 5120 | Author: 镜子 | Hits:

[Special Effects] H264

Description: h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
Platform: | Size: 99328 | Author: 陈成 | Hits:

[VHDL-FPGA-Verilog] 5_lined_cpu

Description: 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
Platform: | Size: 1024 | Author: 张健 | Hits:

[VHDL-FPGA-Verilog] waterline_adder

Description: 这是一个用Verilog编写的四级流水线加法器-This is a Verilog prepared with four pipeline adder
Platform: | Size: 1024 | Author: 伊莲幽梦 | Hits:

[VHDL-FPGA-Verilog] arm7

Description: ARM7 VERILOG源码，非常精简，3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline
Platform: | Size: 173056 | Author: hcq | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
Platform: | Size: 1735680 | Author: era | Hits:

[VHDL-FPGA-Verilog] pipelALU

Description: pipeline ALU verilog code
Platform: | Size: 2048 | Author: holyhi | Hits:

[VHDL-FPGA-Verilog] Conversion

Description: pipeline test in verilog
Platform: | Size: 1024 | Author: buni | Hits:

[VHDL-FPGA-Verilog] PIPELINE

Description: 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.
Platform: | Size: 8720384 | Author: zzh | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 以Verilog撰寫而成的Booth’s Algorithm Multiplier，並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
Platform: | Size: 8192 | Author: Brandon | Hits:

[VHDL-FPGA-Verilog] 64point_FFT

Description: 64-point Pipeline FFT，包含Verilog语言编写的64点FFT运算rtl级程序以及测试程序，此外，还包含设计文档。-64-point Pipeline FFT, Verilog language includes a 64 point FFT computation rtl-level procedures and testing procedures, in addition, includes the design documents.
Platform: | Size: 1249280 | Author: 小飞 | Hits:

[VHDL-FPGA-Verilog] Pipeline-2.zip

Description: Pipeline processor verilog components ,Pipeline processor verilog components
Platform: | Size: 3072 | Author: Aria | Hits:

[VHDL-FPGA-Verilog] Pipeline-3.zip

Description: Verilog codes for pipelined processor,Verilog codes for pipelined processor
Platform: | Size: 3072 | Author: Aria | Hits:

[Software Engineering] 8-grade-4-pipeline-adder-Verilog

Description: 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
Platform: | Size: 13312 | Author: 晨晨 | Hits:

[MPI] pipeline

Description: 一个流水线设计提高FPGA运行主频的实例-a pipeline demo for FPGA written with verilog
Platform: | Size: 72704 | Author: 周彦宏 | Hits:
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